1. Field of the Invention
The present invention relates to a data processor having pipeline processing mechanism, more particularly, to a data processor having operand bypass mechanism for efficiently fetching operand and executing multistage pipeline processing operation with high efficiency.
2. Description of the Prior Art
FIG. 1 is an example of schematic diagram of a pipeline processing mechanism used for a conventional data processor.
Reference numerals in the figure designate the following elements: 11, instruction fetch stage (IF stage); 12, instruction decoding stage (D stage); 13, operand address calculation stage (A stage); 14, operand fetch stage (F stage); and 15, instruction execution stage (E stage).
The IF stage 11 fetches instruction code from a memory and outputs it to the D stage 12. The D stage 12 decodes the instruction code received from the IF stage 11 and outputs a decoding result to the A stage 13.
The A stage 13 calculates an effective address of operand designated in the instruction code, and then outputs the calculated operand address to the F stage 14. In accordance with the operand address delivered from the A stage 13, the F stage 14 fetches an operand from memory. The fetched operand is delivered to E stage 15. The E stage 15 executes arithmetical operation designated by instruction code for the operand delivered from the F stage 14. It also stores the result of arithmetical operation in memory as required.
The pipeline processing mechanism mentioned above divides the processings designated by each instruction into five stages. By sequentially executing five-step processings, all the designated processing are completed. Each of five processings can be implemented in parallel with each other against different instructions. Ideally, compared to the case where no pipeline processing is executed, the five-stage pipeline processing mechanism mentioned above simultaneously processes five instructions so that an efficient data processor having a maximum of 5-times data processing capability can be provided.
As mentioned above, the pipeline processing mechanism has a possibility of greatly promoting data processing capability of data processors, and thus, is widely made available for achieving high-speed data processing operation.
When executing multistage pipeline processing operation mentioned above, even when an operand to be prefetched by the F stage 14 and another operand to be subject to writing-in processing by E stage 15 are identical to each other, the F stage 14 preliminarily fetches the operand from memory, and thus, one time of read access for memory is necessary.
To compensate for this, Japanese Patent Application Laid-Open No. 59-177654 (1984) and Japanese Patent Application Laid-Open No. 61-294550 (1986) for example have been proposed.
Of these, the former invention proposes an art for allowing the following instruction to use register for calculation of addresses, where register is rewritten according to the result of the execution of the preceding instruction. In this case, after completing of rewriting register upon completion of the execution of the preceding instruction, the following instruction executes address calculation. This invention aims at saving time needed for waiting by directly transmitting data, which is written into register, to address calculation unit via bypass route.
On the other hand, the latter invention introduces a constitution in which, when the following instruction had the identical address, data is rewritten by accessing the preliminarly fetched operand from data queue.
Nevertheless, both of these inventions need to access data, and as a result, data processing time is not saved in the actual case.